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az100lvel16vt ecl/pecl oscillator gain stage & buffer with selectable enable 1630 s. stapley dr., suite 127 ? mesa, arizona 85204 ? usa ? (480) 962-5881 ? fax (480) 890-2541 www.azmicrotek.com arizona microtek, inc. package availability package part number marking notes mlp 8 (2x2x0.75) az100lvel16vtna p9 1,2,3 mlp 8 (2x2x0.75) rohs compliant / lead (pb) free az100lvel16vtna+ p9+ 1,2 mlp 8 (2x2x0.75) AZ100LVEL16VTNB p8 1,2,4 mlp 8 (2x2x0.75) rohs compliant / lead (pb) free AZ100LVEL16VTNB+ p8+ 1,2 mlp 8 (2x2x0.75) az100lvel16vtnc p2 1,2,5 mlp 8 (2x2x0.75) rohs compliant / lead (pb) free az100lvel16vtnc+ p2+ 1,2 mlp 8 (2x2x0.75) az100lvel16vtnd p3 1,2 mlp 8 (2x2x0.75) rohs compliant / lead (pb) free az100lvel16vtnd+ p3+ 1,2 mlp 16 (3x3) az100lvel16vtl azm 16t 1,2 mlp 16 (3x3) rohs compliant / lead (pb) free az100lvel16vtl+ azm+ 16t 1,2 die az100lvel16vtxp n/a 6 1 add r1 at end of part number for 7 inch (1k parts), r2 for 13 inch (2.5k parts) tape & reel. 2 date code format: ?y? or ?yy? fo r year followed by ?ww? for week. 3 parts marked tna for date codes prior to 4ww (prior to 2004). 4 parts marked tnb for date codes prior to 4ww (prior to 2004). 5 parts marked tnc for date codes prior to 4ww (prior to 2004). 6 waffle pac k features ? high bandwidth for 1ghz ? similar operation as az100lvel16vr except in disabled condition: q hg is high ? operating range of 3.0v to 5.5v ? minimizes external components ? selectable enable polarity and threshold (cmos/ttl or pecl) ? available in a 3x3 mm or 2x2 mm mlp package ? s-parameter (.s2p) and ibis model files available on arizona microtek website description the az100lvel16vt is a specialized oscillator gain stage with high gain output buffer including an enable. the q hg /q hg outputs have a voltage gain several times greater than the q/q outputs. mlp 16, 3x3 mm package (vtl) or die (vtx) the az100lvel16vtl and az100lvel16vtx provide a selectable enable input (en) that allows continuous oscillator operation. see truth table for the enable function. if enable pull-up is desired in the cmos/ttl mode, an external 20 k resistor connecting en to v cc will override the on-chip pull-down resistor. when disabled, the q hg output is forced high and the q hg output is forced low. the az100lvel16vtl/vtx also provides a v bb and 470 internal bias resistors from d to v bb and d to v bb . the v bb pin can support 1.5 ma sink/source current. bypassing v bb to ground with a 0.01 f capacitor is recommended. the outputs q and q each have a selectable on-chip pull-down curre nt source. see truth table below for current source functions. external resistors may also be used to increase pull-down current to a maximum total of 25 ma.
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 2 outputs q hg and q hg each have an optional on-chip pull-down cu rrent source of 10 ma. when pad/pin v eep is left open (nc), the output current sources are disabled and the q hg /q hg operate as standard pecl/ecl. when v eep is connected to v ee , the current sources are activated. the q hg /q hg pull-down current can be decreased, by using a resistor to connect v eep to v ee . (see graph on page 5.) mlp 8, 2x2 mm package, vtna, vtnb, vtnc & vtnd versions all mlp 8, 2x2mm versions of the az100lvel16vt provide an enable input that allows continuous oscillator operation. vtna and vtnb utilize an enable (en ) that operates in the pecl/ecl mode. when the en input is low, the q and q hg /q hg outputs follow the data inputs. when en is high, the q hg output is forced high and the q hg output is forced low. vtnc and vt nd utilize an enable (en) that oper ates in the cmos/ttl mode. when the en input is high, the q and q hg /q hg outputs follow the data inputs. when en is low, the q hg output is forced high and the q hg output is forced low. for vtna and vtnd, both d and d inputs are brought out and tied to the v bb pin through 470 internal bias resistors. in vtnb and vtnc, the d input is internally tied directly to the v bb pin and the d input is tied to the v bb pin through a 470 internal bias resistor. bypassing v bb to ground with a 0.01 f capacitor is recommended. all mlp 8, 2x2mm versions (vtna, vtnb, vtnc & vtnd) have the q, q hg , and q hg current sources disabled, while the q output operates with a 4 ma current source to v ee . note: specifications in the ecl/pecl tables are valid when thermal equilibrium is established. enable truth table mlp 16 (vtl) or die (vtx) en-sel en q/q q hg q hg nc nc pecl low, v ee or nc pecl high or v cc data data data high data low v ee * v ee * v ee * v ee * cmos low or v ee cmos high or v cc nc, no external pull-up nc, with 20k to v cc data data data data high data high data low data low data *connections to v cc or v ee must be less than 1 . current source truth table mlp 16 (vtl) or die (vtx) cs-sel q q nc v ee * v cc * 4ma typ. 8ma typ. 0 4ma typ. 8ma typ. 4ma typ. *connections to v cc or v ee must be less than 1 . pin description pin function d/d data inputs q/q data outputs q hg /q hg data outputs w/high gain v bb reference voltage output en-sel selects enable logic en/en enable input cs-sel selects q and q current source magnitude v eep optional q hg and q hg current sources v ee negative supply v cc positive supply q d 4ma ea. 470 v bb en v ee en-sel v eep cmos / ttl threshold 10ma ea. cs-sel q hg q d q hg mlp 16 (vtl) or die (vtx) 470
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 3 absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic rating unit v cc pecl power supply (v ee = 0v) 0 to +8.0 vdc v i pecl input voltage (v ee = 0v) 0 to +6.0 vdc v ee ecl power supply (v cc = 0v) -8.0 to 0 vdc v i ecl input voltage (v cc = 0v) -6.0 to 0 vdc i out output current q hg /q hg --- continuous --- surge output current q/q --- continuous --- surge 50 100 25 50 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c 100k ecl dc characteristics (v ee = -3.0v to -5.5v, v cc = gnd) -40 c 0 c 25 c 85 c symbol characteristic min max min max min max min max unit v oh output high voltage 2 -1045 -835 -995 -835 -995 -835 -995 -835 mv v oh output high voltage 4 -1085 -880 -1025 -880 -1025 -880 -1025 -880 mv v ol output low voltage 2,4 -1925 -1555 -1900 -1620 -1900 -1620 -1900 -1620 mv v ih input high voltage d/d , en/en (pecl) en (cmos/ttl) -1165 v ee +2000 -880 v cc -1165 v ee +2000 -880 v cc -1165 v ee +2000 -880 v cc -1165 v ee +2000 -880 v cc mv v il input low voltage d/d , en/en (pecl) en (cmos/ttl) -1810 v ee -1475 v ee + 800 -1810 v ee -1475 v ee + 800 -1810 v ee -1475 v ee + 800 -1810 v ee -1475 v ee + 800 mv v bb reference voltage -1390 -1250 -1390 -1250 -1390 -1250 -1390 -1250 mv i il input low current en 3 0.5 0.5 0.5 0.5 a i ih input high current en 3 150 150 150 150 a i ee power supply current 1 48 48 48 54 ma 1. specified with v eep and cs-sel open for vtl and vtx. subtract 4ma for vtna, vtnb, vtnc & vtnd. 2. specified with v eep and cs-sel connected to v ee for vtl and vtx only. 3. specified with en-sel open for vtl and vtx only. 4. specified with q hg /q hg connected with 50 ? to v cc ?2v for vtna, vtnb, vtnc & vtnd. 100k lvpecl dc characteristics (v ee = gnd, v cc = +3.3v) -40 c 0 c 25 c 85 c symbol characteristic min max min max min max min max unit v oh output high voltage 1,3 2255 2465 2305 2465 2305 2465 2305 2465 mv v oh output high voltage 1,5 2215 2420 2275 2420 2275 2420 2275 2420 mv v ol output low voltage 1,3,5 1375 1745 1400 1655 1480 1680 1400 1680 mv v ih input high voltage d/d , en/en (pecl) 1 en (cmos/ttl) 2135 2000 2420 v cc 2135 2000 2420 v cc 2135 2000 2420 v cc 2135 2000 2420 v cc mv v il input low voltage d/d , en/en (pecl) 1 en (cmos/ttl) 1490 gnd 1825 800 1490 gnd 1825 800 1490 gnd 1825 800 1490 gnd 1825 800 mv v bb reference voltage 1 1910 2050 1910 2050 1910 2050 1910 2050 mv i il input low current en 4 0.5 0.5 0.5 0.5 a i ih input high current en 4 150 150 150 150 a i ee power supply current 2 48 48 48 54 ma 1. for supply voltages other that 3.3v, use the ec l table values and add supply voltage value. 2. specified with v eep and cs-sel open for vtl and vtx. subtract 4ma for vtna, vtnb, vtnc & vtnd. 3. specified with v eep and cs-sel connected to v ee for vtl and vtx only. 4. specified with en-sel open for vtl and vtx only. 5. specified with q hg /q hg connected with 50 ? to v cc ?2v for vtna, vtnb, vtnc & vtnd.
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 4 q hg q d en (vtl, vtx) ; en (vtna, vtnb) (pecl) (cmos) q q hg timing diagram en (vtl, vtx, vtnc, vtnd) 100k pecl dc characteristics (v ee = gnd, v cc = +5.0v) -40 c 0 c 25 c 85 c symbol characteristic min max min max min max min max unit v oh output high voltage 1,3 3955 4165 4005 4165 4005 4165 4005 4165 mv v oh output high voltage 1,5 3915 4120 3975 4120 3975 4120 3975 4120 mv v ol output low voltage 1,3,5 3075 3445 3100 3338 3100 3338 3100 3338 mv v ih input high voltage d/d , en/en (pecl) 1 en (cmos/ttl) 3835 2000 4120 v cc 3835 2000 4120 v cc 3835 2000 4120 v cc 3835 2000 4120 v cc mv v il input low voltage d/d , en/en (pecl) 1 en (cmos/ttl) 3190 gnd 3525 800 3190 gnd 3525 800 3190 gnd 3525 800 3190 gnd 3525 800 mv v bb reference voltage 1 3610 3750 3610 3750 3610 3750 3610 3750 mv i il input low current en 4 0.5 0.5 0.5 0.5 a i ih input high current en 4 150 150 150 150 a i ee power supply current 2 48 48 48 54 ma 1. for supply voltages other that 5.0v, use the ec l table values and add supply voltage value. 2. specified with v eep and cs-sel open for vtl and vtx. subtract 4ma for vtna, vtnb, vtnc & vtnd. 3. specified with v eep and cs-sel connected to v ee for vtl and vtx only. 4. specified with en-sel open for vtl and vtx only. 5. specified with q hg /q hg connected with 50 ? to v cc ?2v for vtna, vtnb, vtnc & vtnd. ac characteristics (v ee = -3.0v to -5.5v; v cc = gnd or v ee = gnd; v cc = +3.0v to +5.5v) -40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit t plh / t phl propagation delay d to q/q outputs 1 (se) d to q hg /q hg outputs 1 (se) 400 550 400 550 400 550 430 630 ps t skew duty cycle skew 2 (se) 5 20 5 20 5 20 5 20 ps v pp minimum input swing 3 diff se 80 160 80 160 80 160 80 160 mv t r / t f output rise/fall times 1 (20% - 80%) 100 260 100 260 100 260 100 260 ps 1. for vtl and vtx, output specified with v eep and cs-sel connected to v ee with an ac coupled 50 load. for vtna, vtnb, vtnc & vtnd, ac coupled 50 on q to v cc ?2v and dc coupled 50 to v cc ?2v on q hg /q hg. 2. duty cycle skew is the difference between a t plh and t phl propagation delay through a device. 3. v pp is the minimum peak-to-peak input swing for which ac parameters guaranteed. the device has a voltage gain of 20 to q/q outputs and a voltage gain of 100 to q hg /q hg outputs.
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 5 bottom center pad may be left open or tied to v ee adjustable high gain output current 0 2 4 6 8 10 12 0 20 40 60 80 100 120 140 160 180 200 v eep to v ee resistor value (ohms) high gain output currents (ma) mlp 16 3x3 mm d 4 3 2 1 58 7 6 10 9 12 11 q nc 13 14 15 16 nc nc cs-sel q hg q hg en-sel en q d v bb v ee v eep v cc top view az100lvel16vtl
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 6 s11, d to q (50 external ac, 4 & 8ma internal dc load on q ) s12, d to q (50 external ac, 4 & 8ma internal dc load on q ) 0.6 0.7 0.8 0.9 1 1.1 1.2 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 frequency (mhz) magnitude -90 -75 -60 -45 -30 -15 0 phase s11 mag 8ma s11 mag 4ma s11 phase 8ma s11 phase 4ma 0 0.01 0.02 0.03 0.04 0.05 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 frequency (mhz) magnitude 70 95 120 145 170 195 phase s12 mag 8ma s12 mag 4ma s12 phase 8ma s12 phase 4ma
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 7 s21, d to q (50 external ac, 4 & 8ma internal dc load on q ) s22, d to q (50 external ac, 4 & 8ma internal dc load on q ) 0.4 0.5 0.6 0.7 0.8 0.9 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 frequency (mhz) magnitude 100 125 150 175 200 225 phase s22 mag 8ma s22 mag 4ma s22 phase 8ma s22 phase 4ma 0 5 10 15 20 25 30 35 40 45 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 frequency (mhz) magnitude -75 -45 -15 15 45 75 105 135 165 195 phase s21 mag 8ma s21 mag 4ma s21 phase 8ma s21 phase 4ma
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 8 bottom center pad may be left open or tied to v ee . pin 4 is the v ee return. bottom center pad is the v ee return. logic diagrams and pinout s for 2x2mm package en operation follows pecl functionality. see timing diagram above. en operation follows pecl functionality. see timing diagram above. d 4ma 470 v bb v ee q hg q q hg mlp 8, 2x2mm AZ100LVEL16VTNB en d 4 3 2 1 6 5 8 7 mlp 8, 2x2mm AZ100LVEL16VTNB q hg q hg en q v bb v ee v cc top view d 4 3 2 1 6 5 8 7 mlp 8, 2x2mm az100lvel16vtna q hg q hg en q v bb v cc top view d v ee d 4ma 470 v bb en v ee q hg q d q hg mlp 8, 2x2mm az100lvel16vtna 470
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 9 bottom center pad may be left open or tied to v ee . pin 4 is the v ee return. en operation follows cmos/ttl functionality. see timing diagram above. d 4ma 470 v bb v ee q hg q q hg mlp 8, 2x2mm az100lvel16vtnc cmos / ttl threshold en d 4 3 2 1 6 5 8 7 mlp 8, 2x2mm az100lvel16vtnc q hg q hg en q v bb v ee v cc top view bottom center pad is the v ee return. d 4 3 2 1 6 5 8 7 mlp 8, 2x2mm az100lvel16vtnd q hg q hg en q v bb v cc top view d v ee d 4ma 470 v bb v ee q hg q d q hg mlp 8, 2x2mm az100lvel16vtnd 470 cmos / ttl threshold en en operation follows cmos/ttl functionality. see timing diagram above. logic diagrams and pinout s for 2x2mm package
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 10 az100lvel16vt die: pad center coordinates name pad designation x(microns) y(microns) a d -342.5 312.5 b d -342.5 144.5 c v bb -342.5 -87.0 d en -342.5 -255.0 e v ee -33.5 -312.5 f v eep 126.5 -312.5 g en-sel 312.5 -248.5 h q hg 312.5 -98.5 i q hg 312.5 51.5 j cs-sel 312.5 201.5 k v cc 302.5 342.5 l q 142.5 342.5 m q -140.5 342.5 a m lk j i h g f e d c b die size: 950u x 950u bond pad: 85u x 85u die thickness: 14 mils lv16vt die pad coordinates
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 11 package diagram mlp 8 2x2mm bottom view side view mlp 8 (2x2mm) 2.0000.050 2.0000.050 pin 1 dot by marking 0.3500.050 pin 1 identification r0.100 typ 1.750 ref. 1.2000.050 exp. pad 1 2 3 4 5 6 7 8 0.2500.050 0.500 bsc 0.6000.050 exp. pad 123 4 0.7500.050 0.000-0.050 0.2030.025 top view note: all dimensions are in mm
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 12 package diagram mlp 16 3x3mm dimensioning and tolerancing conform to asme t14-1994. the terminal #1 and pad numbering convention shall conform to jesd 95-1 spp-012. dimension b applies to metallized pad and is measured between 0.25 and 0.30 mm from pad tip. coplanarity applies to the exposed pads as well as the terminals. notes: 1. 2. 3. 4. d e aaa 2 x c d 2 e 2 b a aaa top view index area (d/2 x e/2) 2 x c 2. d2 d2/2 e2/2 e2 l e 3 x e 3 x bbb bottom view c a b 3. e 1 2 m 5. inside corners of metallized pad may be square or rounded 5. 16 x b dim min max a a1 a3 b d d2 e e2 e l aaa bbb ccc 0.80 0.00 0.18 2.90 0.25 2.90 0.25 0.30 1.00 0.30 0.50 0.25 ref 0.50 bsc 0.25 0.10 0.10 millimeters 0.05 3.10 1.95 3.10 1.95 a a1 a3 side view c seating plane 0.08 c ccc c 4.
az100lvel16vt april 2007 * rev - 9 www.azmicrotek.com 13 arizona microtek, inc. reserves the right to change circuitry a nd specifications at any time without prior notice. arizona mic rotek, inc. makes no warranty, representation or guarant ee regarding the suitability of its products for any particular purpose, nor does a rizona microtek, inc. assume any liability arising out of the applica tion or use of any product or ci rcuit and specifically disclaims any and all liability, including without limitation special, consequential or inci dental damages. arizona microtek, inc. does not convey a ny license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as component s in systems intended to support or sustain life, or for any other application in which the fa ilure of the arizona microtek, inc. product could create a situation where personal injury or death may occur. should buye r purchase or use arizona microtek, inc. products for any such unintended or unauthorized application, buyer shall in demnify and hold arizona microtek, inc. and its officers, employees, subsidiaries, affiliates, and distributor s harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.

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